A considerable consensus has been reached that cache coherence will continue to be employed in future large-scale systems. With the rapid increase in the number of cores on chip, the scalability of a coherence protocol is highly challenging, and maintaining coherence for hundreds or thousands of cores will be unprecedentedly difficult. Although directory coherence protocols offer a relatively practical approach, there is growing concern that simply applying the directory coherence to many-core domain will face serious power and area issues.